Section 1
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01-Introduction (5:41)
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02-Continuous-Time signal (1:55)
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03-Discrete-Time Signal (1:33)
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04-Signal Representation (3:36)
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05-Unit Sample Sequence (2:49)
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06-Unit Step Sequence (3:14)
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07-Analog-to-Digital conversion (9:53)
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08-Digital-to-Analog (3:23)
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09-Quantization Error SRN, SINAD-Part1 (6:42)
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09-Quantization Error SRN, SINAD-Part2 (9:43)
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Section 2
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01-Introduction to Digital Filter (5:22)
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02-FIR general architecture (6:46)
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03-Mobile Average Filter-lecture (5:09)
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03-Mobile Average Filter-sim (8:43)
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04-Frequency response (3:38)
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04-Frequency response-example (4:22)
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05-Impulse response (6:22)
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05-Impulse response-example (4:18)
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06-Step Response (4:54)
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06-Step Response-example (2:36)
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Section 2 material Download
Section 3
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01-Introduction to Fixed point arithmetic (12:10)
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02-Floating point - Fixed Point (7:22)
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03-Fixed point representation (8:18)
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04-Adder-Lecture (10:05)
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04-Adder-VHDL Simulation (19:52)
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05-Subtraction-Lecture (2:32)
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06-Multiplier-Lecture part 1 (3:51)
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06-Multiplier-Lecture part2 (3:56)
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06-Multiplier-VHDL simulation (14:28)
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VHDL Exercise Download
Sectrion 4 - Coming Soon
Section 5
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01-VHDL implementation of Mobile Average Filter-Lecture (4:17)
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01-VHDL implementation of Mobile Average Filter-VHDL simulation (plain implementation) (14:22)
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01-VHDL implementation of Mobile Average Filter-VHDL Simulation (FIR like) (4:21)
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01-VHDL implementation of Mobile Average Filter-VHDL (optimized implementation) (5:36)
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02-VHDL implementation of a classic FIR-Lecture (3:42)
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02-VHDL implementation of a classic FIR-VHDL Simulation (14:53)
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03-VHDL implementation of a symmetric FIR-Lecture (3:47)
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03-VHDL implementation of a symmetric FIR-VHDL simulation (6:16)
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04-VHDL implementation of a antisymmetric FIR-Lecture (2:00)
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04-VHDL implementation of a antisymmetric FIR-VHDL simulation (2:32)
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05-VHDL implementation of a CNN Kernel-Lecture (5:52)
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05-VHDL implementation of a CNN Kernel-VHDL simulation (13:29)
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VHDL Exercise Download
Section 6 - Coming Soon
Section BONUS - Coming Soon
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