Mastering DSP in VHDL

Learn How to Implement High Speed Digital Signal Processing in FPGA using VHDL

  Enroll in Course

Digital Signal Processing is present in every device we use in our daily life.

Most of the DSP algorithms are implemented in software using CPU and GPU.
When the real-time request is demanding no software approach can be used.
In high-speed signal processing environment FPGA or ASIC shall be used.
Design high-speed architecture for digital signal processing is a skill required in the modern Hardware Developer world.
Machine Learning (ML), Artificial Intelligence (AI), Digital Modem, Image Processing, Data Mining are only some examples where Digital Signal Processing skills are mandatory.
In this course, you can find the information you need to start and master the Digital Signal Processing in VHDL.

We start from the Analog to digital conversion and will get to implement complex hardware architecture like FIR, CNN kernel, Decimator Filter, Upsampling filter using VHDL.
All these architectures can be implemented in FPGA or ASIC.
Section 1
  1. Introduction
  2. continuous-time signal
  3. discrete-time signal
  4. Signal Representation
  5. Unit Sample Sequence
  6. Unit Step Sequence
  7. Analog-to-Digital Conversion
  8. Digital-to-Analog Conversion
  9. Quantization error, SRN, SINAD
  10. Section 1 - Course Material


Section 2

  1. Introduction to Digital Filter
  2. FIR general architecture
  3. Mobile Average Filter - lecture
  4. Mobile Average Filter - Simulation
  5. Frequency responce
  6. Frequency response - example
  7. Impulse response
  8. Impulse response - example
  9. Step response
  10. Step response - example
  11. Section 2 - Course material

Section 3

  1. Introduction to Fixed point arithmetic
  2. Floating point-> Fixed point
  3. Fixed point representation
  4. Adder - lecture
  5. Adder - Simulation
  6. Subtraction - lecture
  7. Subtraction - simulation
  8. Multiplier - lecture
  9. Multiplier - -Simulation
  10. VHDL exercise download

Section 4 (to be published)
  • Filter synthesis using Matlab/Octave
  • Remez
  • Fixed point verification Matlab/Octave/C++

Section 5

  1. VHDL implementation of Mobile Average Filter - lecture
  2. VHDL implementation of Mobile Average Filter - implementation
  3. VHDL implementation of Mobile Average Filter - implementation 2
  4. VHDL implementation of Mobile Average Filter - optimised
  5. VHDL implementation of classic FIR
  6. VHDL implementation of classic FIR - simulation
  7. VHDL implementation of a symmetric FIR
  8. VHDL implementation of a symmetric FIR - simulation
  9. VHDL implementation of an antisymmetric FIR
  10. VHDL implementation of an antisymmetric FIR - simulation
  11. VHDL implementation of CNN kernel
  12. VHDL implementation of CNN kernel - simulation
  13. VHDL exercise download

Section 6 (to be published)
  • Introduction to multi-rate filter
  • Interpolation
  • FIR Interpolator
  • Decimation
  • FIR Decimation
  • Fractional interpolation/Decimation

Section 7 (BONUS) (to be published)



Your Instructor


SURF-VHDL
SURF-VHDL

Surf-VHDL supports FPGA/ASIC junior and, why not, senior hardware designers in finding examples and useful hints for their VHDL designs.

My target is to enable you to “surf” the VHDL: I made the VHDL learning experience as simple as it can be.

I'm sharing with you everything that actually helped me in mastering the VHDL.

The website contains many examples, explaining “how to” prepare the most common VHDL constructs, together with one section listing the “common mistakes” in VHDL design.
I strongly believe in knowledge sharing as one of the most important means to improve this world.
I would very much appreciate your cooperation either by submitting your questions or by sharing the link to the website with your friends and colleagues

Enjoy the experience !

Francesco


Course Curriculum


  Section 1
Available in days
days after you enroll
  Section 2
Available in days
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  Section 3
Available in days
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Frequently Asked Questions


When does the course start and finish?
The course starts now and never ends! It is a completely self-paced online course - you decide when you start and when you finish.
How long do I have access to the course?
How does lifetime access sound? After enrolling, you have unlimited access to this course for as long as you like - across any and all devices you own.
What if I am unhappy with the course?
We would never want you to be unhappy! If you are unsatisfied with your purchase, contact us in the first 30 days and we will give you a full refund.
What do I need to know before starting the course?
You need know: VHDL syntax (mandatory) C++ and Matlab (optional). The basic of signal processing theory (optional). Desire to learn (mandatory)

Get started now!