When you use an FPGA you always need a clock unless you are implementing a huge asynchronous logic....
in this case your design need to be deeply revised.
After the VHDL simulation you are ready to start test the design on a board.
Program the FPGA and when you start the debug of your VHDL often your design doesn't work as it should!
Did it happen to you?
It is normal, you should be aware when your design works at the first run :)
Generally the main issue when you test your FPGA and it doesn't work are:
It could be strange but it is true!
In this course you will learn how to use the FPGA itself to check the clock inside your VHDL design.
Surf-VHDL supports FPGA/ASIC junior and, why not, senior hardware designers in finding examples and useful hints for their VHDL designs.
My target is to enable you to “surf” the VHDL: I made the VHDL learning experience as simple as it can be.
I'm sharing with you everything that actually helped me in mastering the VHDL.
The website contains many examples, explaining “how to” prepare the most common VHDL constructs, together with one section listing the “common mistakes” in VHDL design.
I strongly believe in knowledge sharing as one of the most important means to improve this world.
I would very much appreciate your cooperation either by submitting your questions or by sharing the link to the website with your friends and colleagues
Enjoy the experience !