Start Learning VHDL Using FPGA
Everything you need to start learning VHDL using an FPGA
Watch Promo Enroll in Course
How many times did you waste your time in finding some examples
used to resolve your VHDL problems and didn't get anything useful?
YES, it is true that we can find a lot of information for free,
but not all the information we get is a good stuff.
We often don't think about to the time we are wasting searching for unuseful information.
After 20 years in FPGA/ASIC VHDL design, I decided to help all the people that want to
learn the basic rules to implement and efficient hardware design using an FPGA.
With this course, you will learn from the basic of VHDL
and you will be able to start a digital design on FPGA in less than two weeks (*)
Here a brief summary of what you will learn about VHDL at the end of the course:
- Entity / Architecture pair definition
- Concurrency
- VHDL Coding Style: Structural, Behavioral, Sequential
- Event and Transaction
- Delay Modeling: Inertial vs Transport delay
- Concurrent Conditional Signal Assignment
- Understanding Driver & Source concept
- Parametric Design: Generics
- VHDL Types and Data object
- VHDL Types of Data Object: Signal, Variable, Constant and FILE
- Type bit vs ulogic vs std_logic
- Signed and Unsigned Data Types
- Type Conversion and Type Casting
- Subtype definition
- Process Statement
- Sequential Conditional Statement: IF and CASE
- Sequential-Iterative Statement: FOR and WHILE
- The Assert Statement
- Sequential WAIT Statement
- Sensitivity List vs WAIT Statement
- Procedure and Function
- Packages
- Concurrent iterative Statement FOR GENERATE
- Concurrent conditional Statement IF GENERATE
- TextIO package: Read/Write from file
- Test bench design and simulation
The most important section is the LAB section.
Only this section worth more than the price of the entire course.
In the LAB section you will learn how to implement:
- Heart-bit design: let's start to use an FPGA with a blinking led
- Seven segment display: write a VHDL code and drive a seven segment display
- UART: learn how to implement the VHDL code for a UART 16650 compatible with internal FIFO
- Command Parser: VHDL design that contains the LABs above. Connect your board to a PC and start communicating with it.
Enjoy the course and start becoming a VHDL designer!
Francesco
P.S.
Feel free to comment and ask for help.
Your feedback is very important to all the student community and is fundamental to get the course better!
(*) I don't have any magic wand, so if you want to enroll the course and learn VHDL, you should follow the lesson and practice with VHDL. In this case, in less than two weeks you will have the information you need to start to be a digital designer.
Your Instructor
Surf-VHDL supports FPGA/ASIC junior and, why not, senior hardware designers in finding examples and useful hints for their VHDL designs.
My target is to enable you to “surf” the VHDL: I made the VHDL learning experience as simple as it can be.
I'm sharing with you everything that actually helped me in mastering the VHDL.
The website contains many examples, explaining “how to” prepare the most common VHDL constructs, together with one section listing the “common mistakes” in VHDL design.
I strongly believe in knowledge sharing as one of the most important means to improve this world.
I would very much appreciate your cooperation either by submitting your questions or by sharing the link to the website with your friends and colleagues
Enjoy the experience !
Francesco